library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity latch_EXMEM is
    port (
        iALU_OUT : in  std_ulogic_vector(15 downto 0);
        oALU_OUT : out std_ulogic_vector(15 downto 0);

        iReg2D : in  std_ulogic_vector(15 downto 0);
        oReg2D : out std_ulogic_vector(15 downto 0);
		
        iRegWA : in  std_ulogic_vector(3 downto 0);
        oRegWA : out std_ulogic_vector(3 downto 0);
		
		iMEMOP : in  std_ulogic_vector(1 downto 0);
		oMEMOP : out std_ulogic_vector(1 downto 0);

        clk    : in std_ulogic;
        rst    : in std_ulogic;
        enable : in std_ulogic
        );
end latch_EXMEM;

architecture Behavioral of latch_EXMEM is
    component latch16
        port (
            i      : in  std_ulogic_vector(15 downto 0);
            o      : out std_ulogic_vector(15 downto 0);
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
    component latch4
        port (
            i      : in  std_ulogic_vector(3 downto 0);
            o      : out std_ulogic_vector(3 downto 0);
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
    component latch6
        port (
            i      : in  std_ulogic_vector(5 downto 0);
            o      : out std_ulogic_vector(5 downto 0);
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
    component latch2
        port (
            i      : in  std_ulogic_vector(1 downto 0);
            o      : out std_ulogic_vector(1 downto 0);
            clk    : in  std_ulogic;
            rst    : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
begin
    
    U_ALU_OUT : latch16 port map(iALU_OUT, oALU_OUT, clk, rst, enable);
    U_REG2D   : latch16 port map(iReg2D, oReg2D, clk, rst, enable);
    U_REGWA   : latch4 port map(iRegWA, oRegWA, clk, rst, enable);
	U_MEMOP	  : latch2 port map(iMEMOP, oMEMOP, clk, rst, enable);

end Behavioral;

